发明名称 FRAME SYNCHRONIZING SYSTEM
摘要 PURPOSE:To shorten a synchronous returning time by obtaining frame synchronization with utilizing the information of a synchronous position for a specified bit. CONSTITUTION:A specified bit G is arranged in each (s)-bit (the bit number of one block) in a frame with a purpose different from frame synchronizing bits F1-F4. Then, the specified bit G is in the position of N0/s in one frame during an N0 bit period F and an (r)-number of the frame synchronizing bits are wholly arranged just after the specified bit G. Such a receiving code sequence is inputted to a block synchronizing circuit 7 and the block synchronization is obtained concerning the specified bit G. The frame synchronization is continuously obtained, however, at such a time, the noticed bit is only the bit just after the specified bit G enough. When the noticed bit and frame synchronizing bit are not coincident, the shift of one block, namely, the shift of (s) bit is executed. Thus, a frame synchronizing position is reached only by the (N0/s-1) number of the (s) bit shift and the synchronous returning time is shortened.
申请公布号 JPH01305633(A) 申请公布日期 1989.12.08
申请号 JP19880134387 申请日期 1988.06.02
申请人 NEC CORP 发明人 OZAKI HIROICHI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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