发明名称 Circuit arrangement for a level detector
摘要 The invention relates to level detectors for the acquisition of alternating voltage signals exceeding a predeterminable amplitude. The level detector comprises two inverters in CMOS-technology, connected to each other via a resistor, an input isolation capacitor and some resistors for circuitry. In integrated circuits which contain inverters in relatively large numbers, otherwise unused inverters can be used in an advantageous way for the construction of level detectors.
申请公布号 DE3817527(A1) 申请公布日期 1989.12.07
申请号 DE19883817527 申请日期 1988.05.24
申请人 HAGENUK GMBH, 2300 KIEL, DE 发明人 SCHOENKE, HERBERT, 2353 SCHUELP, DE
分类号 G01R19/165 主分类号 G01R19/165
代理机构 代理人
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