| 摘要 |
PURPOSE:To realize slow decoding by carrying out bit rotation processing corresponding to the value of parameter data different from input data for respective data when input data is divided into plural data and amalgamated. CONSTITUTION:The input 32-bit data A is divided into 8-bit data A1-A4. The intermediate keys Kt of the data A2 and A3 are added together by bit-by-bit exclusive OR operation. Further, the data A1 is added to the data A2 by exclusive OR operation and the data A4 is added to the data A3 respectively. Then the data A2 and A3 are added together and 1 is further added; and counterclockwise rotation processing is performed from SALT by the number of bits corresponding to values 0-7 to obtain new data A2. For the data A3, the data A3 and A2 are added and counterclockwise rotation processing is performed by the number of bits corresponding to values 0-7 to obtain new data A3. For the data A1 and A4, similar processing is performed to obtain 32-bit output data. |
