发明名称 PHASE LOCKED OSCILLATOR
摘要 PURPOSE:To maintain an output frequency at the same value as that of the frequency before input discontinuation takes place even when the input signals are discontinued by adding a phase comparator circuit, count circuit, D/A converter, clock interruption detection circuit, clock generation circuit, gate circuit, and voltage sum circuit to the conventional circuit. CONSTITUTION:In a normal state, no phase error occurs among input-output signals by the effect of the 2nd loop. When input signals are discontinued, the clock interruption detection circuit 50 detects the interruption of input clocks and gives a control signal to the gate circuit 60 so as to cause the circuit 60 to inhibit clock signals from the clock generation circuit 40. As a result, no clock signal is given to the count circuit 20 after the discontinuation of the input signals and the count value before the input discontinuation takes place is maintained. Accordingly, the output voltage of the D/A converter 30 which converts the output signal of the circuit 20 into an analog voltage also maintains the value before the input discontinuation takes place. Therefore, the output frequency becomes the same as that before the input discontinuation takes place even after the input discontinuation occurs since the control voltage of a voltage-controlled oscillator 4 which is a summed result does not change also.
申请公布号 JPH01300716(A) 申请公布日期 1989.12.05
申请号 JP19880133481 申请日期 1988.05.30
申请人 NEC CORP 发明人 MUTO HIROSHI
分类号 H03L7/087;H03L7/08;H03L7/14 主分类号 H03L7/087
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