| 摘要 |
<p>PURPOSE:To decrease the circuit scale in case of forming a multiinput bit synchronizing circuit by using a clock of plural phases so as to constitute the bit synchronizing circuit. CONSTITUTION:A quadruple clocks whose phase differs by 90 deg. each are given to clock input terminals PHI1-PHI4 and a data with a deviated phase of a clock is given to a data input terminal due to a delay by a logic circuit and a wire. when the clocks PHI1, PHI2 are extracted at the leading of the data by a phase comparator circuit 103, since D flipflops (DFs) 201, 202 output 0, 0 respectively, it is discriminated that the change point of data exists in the range of 90 deg. to 180 deg. based on the clock PHI1. Thus, a selector 101 is controlled so as to select the clock PHI2 as the data extraction clock. The data extracted by the clock PHI2 by a DF 102 is outputted while the phase is matched with the clock PHI1 at the DF 105. Thus, the bit synchronizing circuit for plural data is realized with small circuit scale.</p> |
