| 摘要 |
PURPOSE:To attain FSK demodulation immune to external disturbance and to eliminate sufficiently the harmonic component after passing through a PLL circuit by connecting an IDF(integration type low pass filter) to an output of the PLL circuit receiving a modulation signal and extracting the demodulation output from the IDF. CONSTITUTION:The major part of the FSK demodulator consists of a multiplier 201 constituting a phase comparator, an LPF 202, a VCO 203 and an IDF 204. Each section consists of delay elements D1 to D4 having a delay time of Tsec (sampling time), an adder and a multiplier or the like. The IDF 204 consists of a delay loop comprising an adder and the delay element D3 and switches SW1, SW2 connecting to the post stage. The switches SW1, SW2 are controlled by a control section 205 in terms of the software and an integration value is outputted sequentially via the switch SW1 at an interval of NT time (corresponding to the baud rate period) and the integration value is reset by the switch SW2 just after the output. Thus, the IDF 204 suppresses the harmonic component superimposed on the output data of the IPF 202. |
