| 摘要 |
<p>A CMOS power-on reset circuit which turns off a reset signal applied to logic circuits only after a power supply voltage reaches a predetermined level when powered up from an inactive state includes a voltage detector stage and a RC delay stage. The voltage detector stage (16) is formed of a first P-channel transistor (P1), a second P-channel transistor (P2), and a first capacitor (C1). The delay stage (18) is formed of a third P-channel transistor (P3) and a second capacitor (C2). The voltage detector stage is used to measure the voltage level of the power supply voltage and generates a control signal. The delay stage is responsive to the power supply voltage and the control signal for inhibiting turn-off of a reset signal at an output node until after the power supply voltage has reached a predetermined level. Logic circuits (14) are provided which respond to the power supply voltage and the reset signal to control logic operations.</p> |
