| 摘要 |
<p>A teletext decoder comprises a validation circuit for affording an output (V) when valid teletext data pulses are received. The validation circuit comprises an error checking circuit (SR, FCCC, MDCC, RACC) for affording outputs indicative of the number of errors existing in data pulses corresponding to a Framing Code, and Hamming protected magazine and row address data, and a validation check circuit (A, VCC) for affording an output V indicative of valid teletext data having been received when the combined total of said errors does not exceed one.</p> |
