发明名称 |
Bidirectional buffer with latch and parity capability. |
摘要 |
<p>A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of birectional bit buffer circuits. Each of the birectional bit buffer circuits includes a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.</p> |
申请公布号 |
EP0344081(A2) |
申请公布日期 |
1989.11.29 |
申请号 |
EP19890480053 |
申请日期 |
1989.04.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BLAND, PATRICK MAURICE;KRAMER, KEVIN GERRARD;DEAN, MARK EDWARD;TEMPEST, SUSAN LYNN;GAUDENZI, GENE JOSEPH |
分类号 |
G06F11/10;G06F13/38;G06F13/40;H03K3/288;H03K19/082 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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