发明名称 |
Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer |
摘要 |
The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
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申请公布号 |
US4884122(A) |
申请公布日期 |
1989.11.28 |
申请号 |
US19880230654 |
申请日期 |
1988.08.05 |
申请人 |
GENERAL ELECTRIC COMPANY |
发明人 |
EICHELBERGER, CHARLES W.;WOJNAROWSKI, ROBERT J.;WELLES, II, KENNETH B. |
分类号 |
G01R31/317;H01L23/538 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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