| 摘要 |
PURPOSE:To continuously supply power to a load without stopping an inverter even when a PLL circuit fails by providing internal oscillating circuits for respective plural inverters and connecting the outputs of the internal oscillating circuits to a common bus. CONSTITUTION:The title device is used by providing internal oscillating circuits 1A and 2A for inverters 1 and 2 respectively, previously connecting the outputs of the circuits 1A and 2A with a common bus (a) and superimposing a reference pulse 20a outputted by a PLL circuit 12 on the bus a. The frequencies of output pulses 10b and 11b of 1/N dividers 10A and 11A are set slightly lower than the frequency of the pulse 20a. Ordinarily, the inverters 1 and 2 are operated by the pulse 20a. At this time, the output pulses 10b and 11b of the dividers 10A and 11A are never outputted because the circuit 12 gives a reset signal as an external reset command to reference oscillators 10 and 11. When the circuit 12 fails, and the output 20a is stopped, either of the output pulses 10b and 11b is selected, the reference pulse is given to inverter control circuits 31 and 41, and the operation of the inverters 1 and 2 are continued. |
