Topographic pattern delineated power MOSFET with profile tailored recessed source.

摘要

A dopant-opaque layer of polysilicon (32) is deposited on gate oxide (26) on a silicon substrate (18, 20) to serve as a pattern definer. It controls successive P and N doping steps used to form operative DMOSFET regions within the substrate, a trench (63) in the silicon surface, and conductive structures (28, 30) atop the substrate. A source conductive layer 28 is deposited in the trench to electrically contact source region (24) as a gate conductive layer (30) is deposited atop the gate oxide 26. The trench sidewall (64, 65) is profile tailored using a novel O2-SF6 plasma etch technique. An oxide sidewall spacer (62) is formed on the sides of the pattern definer (32) and gate oxide (26), before depositing the conductive material (28, 32). A planarizing layer (72) is used as a mask for selectively removing any conductive material deposited atop the oxide spacer.