发明名称 APPARATUS FOR ERROR CORRECTION
摘要 In an apparatus for error correction in which data sequences containing blocks each formed of plural data words previously arranged on a time-base and check words are written in a data memory (37) on the basis of a write address generator (38), the data sequences are then read out from the data memory (37) on the basis of a read address generator (39) so as to generate rearranged data sequences and, during writing and reading of the data sequences, error correction is carried out, there is included an error correction arithmetic circuit (50) for performing an error correction calculation, a pointer addition circuit (51, 52) for adding a pointer to the data words in association with an error state of the blocks, and a program memory (49) for memorizing a microprogramm with fields to control the error correction arithmetic circuit (50) and pointer addition circuit (51, 52).
申请公布号 DE3380752(D1) 申请公布日期 1989.11.23
申请号 DE19833380752 申请日期 1983.01.19
申请人 SONY CORPORATION 发明人 FURUYA, TSUNEO C/O PATENT DIVISION;FUKAMI, TADASHI C/O PATENT DIVISION
分类号 G06F11/10;G11B5/09;G11B20/18;H03M13/00;H03M13/27;(IPC1-7):G11B5/09 主分类号 G06F11/10
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