| 摘要 |
<p>PURPOSE:To prevent erroneous writing due to the stress of electrostatic discharge (ESD) by connecting a terminal, to which a writing voltage is added from an external part, and the source of a transistor for writing through an MOS transistor. CONSTITUTION:A Vpp terminal 1, to which a writing voltage Vpp is added from the external part, and the source of a transistor TW for writing are connected through MOS transistors 4 and 5. Accordingly, when the ESD stress is added to the Vpp terminal 1, since the MOS transistors 4 and 5 exist, this stress is not added to the source of the transistor TW for writing as it is. At such a time, even when the MOS transistors 4 and 5 are temporarily turned on, since the MOS transistors 4 and 5 are turned off in case that the source potential of the transistor TW for writing slightly rises up by charging, the source potential does not rise up moreover. Thus, the erroneous writing of a memory cell can be prevented.</p> |
