| 摘要 |
PURPOSE:To minimize the data transmission error without increasing the manufacture cost by providing a circuit adding a start bit to the head of a sent serial data signal and detecting the start bit to the next to the final stage of a shift register of a receiver side equipment. CONSTITUTION:The start bit comprising 1 bit or over is added to the head of a serial data signal. Moreover, number of flip-flop circuits 7 coincident with bit number of the start bits are connected in series with the digit next to the final digit of the shift register 4. When the head bit is shifted to the flip-flop circuits 7, the 1st logic circuit 8 is set and a fetch command signal is sent to a reception buffer 9, which fetches each bit data stored in each digit of the shift registers 4 simultaneously and outputs the result as a parallel data signal. Since the start bit is given to the 2nd logic circuits 5a-5h as soon as the fetch command signal is sent from the 1st logic circuit 8, the input signal to each digit of the shift registers 4 is cleared. Thus, the data transmission error is minimized without increasing the manufacture cost. |
