发明名称 ASYNCHRONOUS CLOCK SELECTING/SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To prevent the pulse and the oscillation that cause a fault having the small width and to ensure the safe and sure working even with a digital circuit using two asynchronous clocks by switching these clocks via a smallest circuit and in the minimum time with no influence given to the output. CONSTITUTION:When the clock selecting signal changes its clock to a 2nd clock from a 1st clock, the means 1 and 2 produce the differential pulses from the selecting signal and the output clock. While a means 9 inhibits a flip-flop 3 which permits the output of the 1st clock by means of logic '1' of the differential pulse and the fall of the 1st clock and permits a flip-flop 4 that inhibited the output of the 2nd clock by means of the inhibiting signal of the flip-flop 3 and the fall of the 2nd clock. In such a constitution, the asynchronous clocks can be switched in the minimum time and with a circuit of the smallest structure with no influence given to the output.
申请公布号 JPH01290013(A) 申请公布日期 1989.11.21
申请号 JP19880119224 申请日期 1988.05.18
申请人 NEC CORP 发明人 NEGISHI IWAO
分类号 H03K5/00;G06F1/04;G06F1/06;H04L7/04 主分类号 H03K5/00
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