Fully synchronous half-frequency clock generator

摘要

A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the serially connected stages are controlled alternatively by a true and a complemented clock signal. Preferably, there are two such loops operating in parallel but which include initialization circuitry that initializes the two loops to complementary values.