| 摘要 |
PURPOSE:To attain difficult decoding of a CPU program by randomizing an address to the CPU program stored into a second ROM and program data with the random data of a first ROM. CONSTITUTION:When the address is outputted from a CPU 1 to an address bus 10, and simultaneously a memory read signal 12 is outputted, a first ROM 3 outputs the random data stored into the address outputted to the bus 10 to a data bus 13 of the ROM 3. Since the data outputted to the bus 13 of the ROM 3 are given to a second ROM 2 as the address, the data at an M bits stored into the address are outputted to a data bus 15 at the M bits of the ROM 2. An exclusive OR circuit 4 obtains the exclusive logical sum of the output data between the low-order M bits of the bus 13 of the ROM 3 and the M bits of the ROM 2, and outputs it to a data bus 11 of the CPU 1. The CPU 1 fetches in the data outputted to the bus 11, and normaly operates them. |
