SEMICONDUCTOR DEVICE WITH DYNAMIC AND STATIC CIRCUIT OF MATCHED TIMING

摘要

The static delay circuit is connected to a clock signal generator and to one stage of a multi-stage dynamic circuit, for delaying the clock signal (PHI) and producing the delayed clock signal (PHI-D). This stage of the multistage dynamic circuit is initiatd by the delayed clock signal. An output circuit is connected to the multistage dynamic circuit and to the static circuit to generate a signal in response to operation of the static circuit which is matched by the operation of the multistage dynamic circuit. The delay circuit provides an inverter(INV1) connected to the clock signal generator and to a second inverter(INV2) which has a load transistor.