| 摘要 |
PURPOSE:To accelerate read/write access to a register by providing a first expander, a byte selector to select and output data in byte unit, and a second expander. CONSTITUTION:Write data is inputted from a main storage 2 to the first expander 4 passing through a third data bus 11, and the expansion of the write data is performed at the first expander 4, and is outputted to a register write data bus 9, and is written on the low-order two bytes of the register 13. Meanwhile, the data of the register 13 is outputted to a register read data bus 28 for a read request. The byte selector 26 selects the low-order two bytes of the third data bus 11 instead of the data on the register read data bus 28 according to a selection signal 16a outputted from a control part 17 to the second expander 25. The data of one valid low-order byte in the data out of the two bytes selected by the byte selector 26 is expanded to two bytes at the second expander 25, and is outputted to a first data bus 10a, and is inputted to an arithmetic unit 3. In such a way, it is possible to make write access to the register at high speed. |
