| 摘要 |
PURPOSE: To output terminal count instruction without an erroneous electric signal by connecting a digital count to an input of a state decoding means of the next stage and a state logic means and the next terminal count decoding means to an output of the same. CONSTITUTION: A counter 100 is provided with the next terminal count decode 125, connected to the output of a next state decode 115 and includes a logic circuit which is preferably in the form of a clock terminal count flip-flop 132 pior to a terminal count enabling means. When the terminal count circuit flip- flop 132 and a logic circuit 130 changes a value simultaneously with the change of a state flip-flop value, the terminal count instruction is provided for all the clock cycles. Therefore, any unerring electric signal due to the delay of the line is set well before any value set in a D-input of the terminal count flip-flop 132 is transferred to a Q-output. |
