TOP STAGGER TYPE AMORPHOUS SILICON THIN-FILM TRANSISTOR ARRAY

摘要

PURPOSE:To lower the resistance value at the junctures of gate wirings and Cr layer by forming the gate wiring terminals of the Cr layer and forming a barrier layer consisting of Ti (titanium) or Ti alloy between said layer and the gate wiring. CONSTITUTION:The gate wiring terminals of the top stagger type amorphous silicon thin-film transistor array formed with the gate wiring consisting of Al are formed of the Cr layer 2 and the barrier layer 3 consisting of the Ti or Ti alloy is formed between the gate wiring 4 and the Cr layer 2. The interdiffusion of the Al and the Cr is, therefore, eliminated and since no alloys are formed, the resistance value does not increase at the junctures between the Cr layer 2 and the barrier layer 3 as well as the gate wiring 4. The resis tance value from the gate wiring terminals to a-SiTFT (thin-film transistor) is thereby maintained at low resistance and signals are faithfully transmitted.