| 摘要 |
The invention relates to a reserve column selection circuit comprising two groups of line interrupters 10, 10' arranged between two reserve input/output line units 4, 4' connected to two reserve bit lines 3, 3' and two normal input/output line units 5, 5' connected to two normal bit lines 6, 6'; the two line interrupter groups are controlled by an output signal phi D from a reserve column decoder 1; two normal line excitation elements 20, 20' are connected to the respective normal input/output line units 5, 5' and are controlled by the output signal phi D from the reserve column decoder; an inverter I1 produces a clock signal phi SCD of inverted phase which controls the link between the two reserve input/output line units and the two reserve bit lines. Application to row/column digital memories. <IMAGE>
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