INTEGRATED CIRCUIT PATTERN EXPOSING METHOD,申请号JP19880114590-传众专利搜索

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发明名称	INTEGRATED CIRCUIT PATTERN EXPOSING METHOD
摘要
申请公布号	JPH01286416(A)	申请公布日期	1989.11.17
申请号	JP19880114590	申请日期	1988.05.13
申请人	NEC CORP	发明人	YANAGIHARA TOSHIAKI
分类号	G03F7/20;H01L21/027;H01L21/30	主分类号	G03F7/20
代理机构		代理人
主权项
地址

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