发明名称 CLOCK CONTROL SYSTEM
摘要 <p>PURPOSE:To improve reliability by stopping the oscillation of a clock signal not used. CONSTITUTION:A clock signal control system has clock oscillating circuits 111 to 112 to respectively output the clock signal the number of vibrations fc1 and fc2 corresponding to two types of the mode, stopping circuits 121 to 122 provided at these respectively, a NAND element 13 and a NOT element 14. When a picture is displayed by the mode to use the clock signal of the number of the vibration fc1 out of two picture displaying modes, the output of the signal of a '0' condition is executed as a switching signal and a clock oscillating circuit 111 is selected. As this result, a said signal, which is inverted by the above-mentioned NOT element 14 and becomes a '1' condition, is inputted to a blocking circuit 122 of an oscillating circuit 112. Thus, the clock signal not used is not outputted and the bad influence to other device can be prevented.</p>
申请公布号 JPH01286008(A) 申请公布日期 1989.11.17
申请号 JP19880114892 申请日期 1988.05.13
申请人 FUJITSU LTD 发明人 ASAHINA YOSHIYUKI
分类号 G06F1/04;G06F1/06 主分类号 G06F1/04
代理机构 代理人
主权项
地址