| 摘要 |
PCT No. PCT/JP84/00307 Sec. 371 Date Feb. 12, 1985 Sec. 102(e) Date Feb. 12, 1985 PCT Filed Jun. 13, 1984 PCT Pub. No. WO85/00066 PCT Pub. Date Jan. 3, 1985.This invention relate to a synchronizing circuit for a data signal in which a data signal is divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an arbitrary address signal and an error detection signal for the address signal and received so as to be written in a memory in accordance with the address signal, which includes means (4) for detecting the synchronizing signal and means (3) for detecting an error of the address signal. The circuit further comprising an interpolation synchronizing signal generating circuit (6) and an interpolation address signal generating circuit (10), in which when the address signal is judged as being correct by the error detecting means (3), the interpolation synchronizing signal generating circuit (6) is driven, the interpolation address signal generating circuit (10) is driven by an interpolation synchronizing signal from the interpolation synchronizing signal generating circuit (6), and the address signal and the interpolation address signal are changed over on the basis of whether the address signal is correct or erroneous and then fed to the memory (13 ). According to this invention, it is possible to establish the synchronization by a circuit of a simple construction. |
