发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To suppress the latch-up phenomenon by particularly increasing the impurity concentration of a buffer layer of an IGBT at a part other than a region immediately below a channel forming region. CONSTITUTION:An N<+>-type buffer layer 11 is epitaxially grown on a substrate which will become a P<+>-type drain region 2, and an N<++>-type buffer layer 12 is formed at a part other than a region immediately below a P-type channel forming region 6 by means of, e.g., ion-implantation. An IGBT is formed by arranging the channel forming region 6, a gate oxide film 4, a polycrystalline Si 5, an N<+>-type source region 7, a drain electrode 1, and a source electrode 8 by epitaxially growing an N<->-type drain region 3. Although holes which cannot be recoupled at the N<->-type drain region 3 are generated in a large current region, the N<++>-type buffer layer 12 has a poor mobility hole injection efficiency, whereby the number of holes moving from the P-type channel region 6 to the electrode 8 via an N<+>-type source region 7 is reduced compared with that of a conventional type structure. As a result, a voltage drop between the source region and the channel forming region is small, thereby suppressing the latch-up phenomenon.
申请公布号 JPH01282872(A) 申请公布日期 1989.11.14
申请号 JP19880112029 申请日期 1988.05.09
申请人 MATSUSHITA ELECTRON CORP 发明人 TANIDA HIROSHI;KAWASHIMA ISAMU
分类号 H01L29/68;H01L29/739;H01L29/78 主分类号 H01L29/68
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