| 摘要 |
PURPOSE:To separate the parasitic capacitor of a common data line and a data line, to relieve the load of a sense amplifier and to quicken the readout by providing a readout amplifier connected directly to the data line. CONSTITUTION:A memory array consists of arrays UM, LM. Signals L, R to select right/left series circuits and a selection signal US for the array UM are supplied to gate circuits G1, G2 and a left series storage circuit is coupled with a data line DO through MOSFETs Q2, Q1. With the signals US, R at an H level, the right series storage circuit is coupled with the line DO. Then the storage information of the storage MOSFET is read by readout amplifier circuits DA0, DA1 as sub sense amplifiers and its amplified output is outputted through a sense amplifier SA and a data output buffer DOB through a common data line CD. |
