发明名称 PAD ARRANGEMENT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To enable the voltage to be measured with high precision without increasing the space of a chip by a method wherein a plurality of voltage measuring sense pads electrically connected to a plurality of bonding pads for signal are arranged in the direction substantially perpendicular to the outer side of a semiconductor integrated circuit chip. CONSTITUTION:Respective voltage circuit measuring pads 4 are electrically connected to bonding pads 2 for signal arranged on edge parts 1a of a semiconductor integrated circuit chip 1 so that, even if the sense pads 4 are supplied with high current in case of a wafer test, the voltage on the bonding pads 2 may be measured through the intermediary of the sense pads 4 and he probes 5 of probe cards. Furthermore, the sense pads 4 opposing to the bonding pads 2 are arranged in the direction perpendicular to the outer side 1b of the semiconductor integrated circuit chip 1 so that the voltage measuring sense pads 4 may be provided restraining the space of the semiconductor integrated circuit chip 1 from increasing. Through these procedures, the voltage can be measured with high precision without increasing the space of the chip 1.
申请公布号 JPH01278033(A) 申请公布日期 1989.11.08
申请号 JP19880106881 申请日期 1988.04.28
申请人 NEC CORP 发明人 NAKASHIBA HIROSHI
分类号 H01L21/60;H01L21/3205;H01L21/66;H01L21/822;H01L23/52;H01L27/04;H03K19/086 主分类号 H01L21/60
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