| 摘要 |
PURPOSE:To efficiently detect zero at a high speed even in case of the increase of the number of bits by simultaneously inputting data of respective bits of a binary to plural stages of condition detecting circuits and performing parallel logical operation to generate a zero detection output signal. CONSTITUTION:A condition detecting circuit 101 has AND circuits, NOR circuits, and EOR circuits to which data A1 and B2 of LSB are inputted respectively and operates NOT-OR of AND between respective output signals of NOR circuits of a condition detecting circuit 102 which are provided correspondingly to a pair of data A2 and B2, AND between respective outputs of NOR circuits of the circuit 101 and AND circuits of the circuit 102, and AND between respective outputs of EOR circuits of the circuit 101 and EOR circuits of the circuit 102. Detection signals S1-Sn of circuits 101-10n are inputted to a decision circuit 30. When signals S1-Sn are all '0', the circuit 30 outputs '1', and n bits of the result of addition between n-bit binary numbers A and B are zero. |
