| 摘要 |
<p>A multi-port cache memory (2) of multi-port memory structure is connected to and shared with a plurality of processors (P0 SIMILAR Pn). The multi-port cache memory may have two sets of interface signal lines (6A-0 SIMILAR 6A-2, 6B-0 SIMILAR 6B-2), for instruction fetch and for data read/write, to each processor. The multi-port cache memory may also be used only for data read/write. The system performance is further improved if a plurality of processors and a multi-port cache memory are fabricated on a single LSI chip.</p> |
