SYNC RESPONSIVE CLOCK GENERATOR FOR DIGITAL DEMODULATORS

摘要

A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects a synchronization code in the input bit stream to derive the frequency error signal by counting the number of clock pulses present in the period of the detected synchronization code.