发明名称 Fast processor for multi-bit error correction codes.
摘要 <p>Apparatus and method for performing error checking (107) and syndrome generation (111) on multibit characters of blocks of messages. The characters are processed ad seriatim and the symbols or syndromes are accumulated until all characters of a block have been processed. The check symbols are concatenated with the associated message block while the check symbols are accumulated for the next block (109). If there is a nonzero syndrome, the accumulated syndromes (115) can be extracted while the syndromes for a next block are being generated.</p>
申请公布号 EP0340139(A2) 申请公布日期 1989.11.02
申请号 EP19890480051 申请日期 1989.04.04
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 NIELSON, MARLIN GRAIG;WOODRUFF, KENNETH R. (NMN)
分类号 G06F11/08;G06F7/72;H03M13/00;H03M13/15;H03M13/27 主分类号 G06F11/08
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