| 摘要 |
<p>PURPOSE:To improve the tracking performance against the fluctuation of a signal of being an object of synchronization by selecting a clock signal whose phase is most matched to a signal of an object of synchronism based on a logic level of plural clock signals whose phase differs from each other at the synchronizing point. CONSTITUTION:Plural clock signals CK1 to CK4 whose phase differs from each other are formed by utilizing delay element groups 61 to 63 and the logic level of the clock signals at the front edge of a horizontal synchronizing pulse of a horizontal synchronizing signal HD is fetched by latch circuit groups 71 to 74. Then the clock signal whose phase is bet matched with that of the horizontal synchronizing signal HD is discriminated through the extraction of the latch circuit groups 71 to 74 and AND circuit groups 81 to 84 based on the logical level state of the front edge. Then the discriminated clock signal is discriminated by AND circuit groups 91 to 94 and an OR circuit 10 and outputs it as a sampling clock signal CKO. Thus, the sampling clock signal whose phase is matched is outputted from the front edge of the horizontal synchronizing pulse.</p> |
