发明名称 CLOCK SELECTOR
摘要 PURPOSE:To delete the number of constitution element by selecting from the surface edge of a clock in order to select a clock at an approximately constant phase with a horizontal synchronizing signal inputted out of a clock signal having a different delaying time and keeping the selected clock as it is or inverting a polarity. CONSTITUTION:By the output of latch circuits 131-135 to latch an output clock with the smallest delaying time out of plural latch circuits 131-135, the output clock of a selecting means 150 is outputted by keeping it as it is or inverting a polarity. Thus, the mose preceding and changed clock for the rise edge of a horizontal synchronizing signal is selected, it is discriminated by the output of latches 131-135 whether the clock change is the rise edge or the fall edge, the polarity of the output clock is determined, and thus, the clock of the approximately constant phase to the horizontal synchronizing signal can be generated. Thus, the delaying quantity of a clock can be halved more than conventionally and the number of the elements to constitute the circuit can be reduced to half.
申请公布号 JPH01272278(A) 申请公布日期 1989.10.31
申请号 JP19880100707 申请日期 1988.04.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAGEYAMA YOSHIKAZU
分类号 H04N5/956;G06F1/06;H03K5/00;H03K5/13;H03K5/133;H04N5/10;H04N5/95 主分类号 H04N5/956
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