| 摘要 |
An erasable programmable logic device which includes a programmable AND memory array and a macrocell processing the output of the AND array allows product term sharing/allocation by adjacent macrocells. Two groups of four product terms each are coupled to each macrocell, wherein the OR'ing of each group of four product terms is each coupled to a multiplexor. One group is also coupled to a previously adjacent macrocell and the second group is coupled to a subsequently adjacent macrocell. A third and fourth multiplexor accept four product terms from each of the adjacent macrocells and the output of the four multiplexors are coupled to an OR gate. When a multiplexor is activated, it couples each grouping of four product terms to the OR gate and the output of the OR gate is coupled to an I/O circuit which emulates combinatory and sequential logic circuits. By selecting appropriate multiplexors each eight product term macrocell is capable of processing 0, 4, 8, 12 or 16 product terms. An alternative embodiment has three groupings of product terms wherein only two of the groupings are shared by adjacent macrocells.
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