| 摘要 |
The invention is directed to a method and circuit for performing an addition operation in successive pipelined instructions which utilize a sliced ALU. Successive microinstructions are monitored to determine if both microinstructions are add operations. Further, it is determined whether the use of the destination of the first microinstruction is a source for the add operation in the second microinstruction. If both microinstructions are add operations and the destination of the first microinstruction is used as the source for the second microinstruction and one of the addends of the second microinstruction is a small addend then the circuit detects whether a carry-out occurred in the least significant slice of the second instruction. If there is no carry-out, the result for the more significant slice of the second microinstruction answer. However, if a carry-out was detected, then the result for the second microinstruction's more significant slice is the sum+1 of the second microinstruction.
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