FLASH-ANALOG TO DIGITAL CONVERTER

摘要

The comparator circuit is arranged to reduce Miller Capacitance between the terminals of collector and base in the latching comparator transistors (Q8, Q9). The circuit comprises the transistors (Q14, Q15) connected to the latching comparator in positive feedback, the level shifters (Q4, Q6) biasing the cascade transistors (Q14, Q15). The reduced Miller brings about an increase in A/D conversion.