| 摘要 |
PURPOSE:To keep a logical simulator in a conventional state and to improve the calculating accuracy of the delay time as a preprocess by using a load/ writing capacity calculating module, a rise/fall time calculating module, etc. CONSTITUTION:When the transmission delay time is calculated, the general load capacity connected to the output terminal of each gate is calculated by a load/wiring capacity calculating module 1 based on the connecting information on a circuit to be analyzed, the data on the wiring capacity, and a delay time calculation library 7. This calculated load capacity is sent to the load capacity calculation result 4. Then a rise/fall time calculating module 2 calculates the rise/fall time of the output signal of each output terminal based on the load capacity and the library 7 and sends this calculated rise/fall time to the rise/fall time calculation result 5. Then a delay time calculating module calculates the delay time of each gate in consideration of the rise/fall time of an input waveform based on both results 4 and 5 and the library 7. Thus the delay tie calculating accuracy is improved as a preprocess with a logical simulator kept in a conventional state. |
