发明名称 COUNTING CIRCUIT
摘要 PURPOSE:To perform the test in a short time by successively sending carry from the first stage to the last stage in respective unit counting circuits at the time of the test mode with respect to a counting circuit where plural unit counting circuits are cascaded. CONSTITUTION:When a test mode setting signal TE sets a counting circuit 10 to the test mode, a signal to be counted is supplied to all unit counting circuits 10 in parallel by a supply means 20 of the signal to be counted until carry CA of the unit counting circuit 10 in the first stage is detected. When carry CA in the unit counting circuit 10 in the preceding stage is detected, supply of the signal to be counted to the unit counting circuit 10 in the next stage is stopped. Therefore, carrying up is successively sent from the first stage to the last stage in respective unit counting circuits. Since unit counting circuits 10 are not disconnected, transmission of the carry signal is easily tested.
申请公布号 JPH01270413(A) 申请公布日期 1989.10.27
申请号 JP19880098177 申请日期 1988.04.22
申请人 ANRITSU CORP 发明人 WATANABE YOSHIHIRO
分类号 H03K21/40 主分类号 H03K21/40
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