| 摘要 |
The phase synchronisation circuit controls a graphic display device in a teletext receiving system. The circuit includes a delay circuit, adapted to delay, in sequence, clock signals which are to be phase-synchronised with a reference signal and to produce, in sequence, delayed clock signals. A selection circuit includes set/ reset circuits and gates. Each gate receives the output of the set/ reset circuits and of the delayed clock signals. Among the delay clock signals, the signal that has the nearest edge timing to the edge of external signals is selected.
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