| 摘要 |
PURPOSE:To facilitate defect analysis of a device by providing a memory NVRAM in which an SRAM and a non-volatile memory EEPROM are integrated into 1 chip, restoring the contents of the EEPROM to the SRAM, and reading them at the time of the device defect analysis. CONSTITUTION:The title unit is equipped with the memory NVRAM (Non volatile SRAM) in which a static random access memory (SRAM)C and an electrically rewritable non-volatile memory (EEPROM)D are integrated into 1 chip. At an ordinary time, reading and writing are executed in a high speed as the ordinary SRAM, and at the time of a power source interruption and a device defect detection, for example, the time of the action output of a protecting relay, the contents of the SRAM C to be stored so far are transferred to the EEPROM D in the NVRAM in a batch. Consequently, plural non-line data, control signals, defect detection results in a certain fixed period can be stored into the non-volatile memory EEPROM D. Thus, a cause, an action output generation state, a time, defect contents, etc., can be easily analyzed. |
