| 摘要 |
<p>Integral linearity error in the operating characteristics of an analog to digital converter employing sampling comparators (12) is reduced by generating a further error in a sense to offset said linearity error at least in part. This is achieved, in a preferred embodiment, by recurrently connecting (31) at least one resistive shunt (28) across a predetermined central portion of a reference voltage divider input (22) to the comparators. The shunt resistance is approximately an order of magnitude larger than the resistance of the shunted part of the divider. Each recurrent connection interval is of fixed duration independent of sampling rate, and each interval spans the beginning of a recurrent time of connection of said divider to said comparators. <IMAGE></p> |
