| 摘要 |
<p>A digital signal processing system for digit serial processing of signals includes a cell stack (10) including a number of individual operation cells (16) equal to the number (n) of digits to be processed in conjunction with cap (12) and control (14) cells to provide power, control and timing signals. The arrangement employed permits the construction of cell libraries for silicon compliers from a small number of individual components and permits such compliers to generate chip fabrication masks for a plurality of fixed, but initially arbitrary, digit size circuit designs.</p> |
