| 摘要 |
<p>A direct digital synthesizer (DDS) accumulator circuit (66) is disclosed wherein a selected few of the low order accumulator bits are dithered by a pseudorandom number generator (21) in order to introduce flat frequency deviation density to suppress spurious signals including those close-in to the output or fundamental frequency. The accumulator circuit (66) may advantageously be sectioned into a lower order accumulator (49) and higher order accumulator (50) in a pipelined combination with a sine approximation output circuit in order to construct a DDS circuit wherein such spur suppression is achieved without decreasing system throughput.</p> |
