| 摘要 |
PURPOSE:To prevent a data breakdown in an area which a CPU desires to protect by providing a bus control part for inhibiting an access to an address which has been outputted from a peripheral device in accordance with a result of comparison of an address comparator at the time of a holding state. CONSTITUTION:When a CPU is in a holding state, an address buffer 6 is switched to an input side, and an address outputted from a peripheral device is latched by a comparator 10 through an address input line 18. On the other hand, an address area protecting register 11 to which a head address and area length of a protection area have been set in advance by an executing part 4 is provided on the inside of the CPU, and the address comparator 10 compares this register data and latch data. When the result coincides, the comparator 10 outputs a coincidence signal 28 to a bus control part 8, and the control part 8 inhibits a bus use by the peripheral device by making a bus permitting signal outputted to the peripheral device inactive, inhibits an access to an output address and protects its address area, and also, allows the executing part 4 to generate an interruption, and the CPU enters into an error processing cycle. |
