发明名称 |
Method of making a static ram cell with trench pull-down transistors and buried-layer ground plate |
摘要 |
Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.
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申请公布号 |
US4876215(A) |
申请公布日期 |
1989.10.24 |
申请号 |
US19880236209 |
申请日期 |
1988.08.23 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
HSU, FU-CHIEH |
分类号 |
H01L21/74;H01L21/8244;H01L23/532;H01L27/11 |
主分类号 |
H01L21/74 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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