A bit packet communication system includes a head-end having a software implemented 16 bit shaft register with a plurality of feed-forward taps and a different plurality of feed-back taps for simultaneously dividing and multiplying the input data bit packet to provide an output bit packet that is both encrypted and error protected. Dynamic encryption is provided by utilizing an initial preset for the software corresponding to a preset encryption key for the shift register. Authorized subscriber terminals are provided with memories and decryption keys are downloaded. The bit packets are assembled with a global bit packet encrypted with a global encryption key and subsequent individually addressed bit packets encrypted with address keys. The address keys and terminal addresses are permanently stored in the subscriber terminal memories. The global encryption keys are changed periodially. Means are provided in each subscriber terminal for storing a number of global decryption keys which are cycled through in attempts to decrypt the global packets. One of the global decryption keys is a permanent default key associated with the subscriber terminal to assure that communication with that terminal is possible despite a lack of knowledge of the terminal address or the other global decryption keys in its memory.
申请公布号
US4876718(A)
申请公布日期
1989.10.24
申请号
US19880221166
申请日期
1988.07.19
申请人
ZENITH ELECTRONICS CORPORATION
发明人
CITTA, RICHARD W.;GOSC, PAUL M.;MUTZABAUGH, DENNIS M.;SGRIGNOLI, GARY J.