| 摘要 |
PURPOSE:To simply inspect an error inspection correcting circuit by providing a data changing means which can change at least one of an information bit and an inspection bit by an instruction of a CPU. CONSTITUTION:By an instruction of a CPU 1, data in a control latch circuit 9 is set to '0', and data Dt1 and a parity bit PB1 are written in an address A1 in an E<2>PROM. Subsequently, the data in the circuit 9 is set to '1', and in a state that a parity bit PB8 has been set to a data latch 8, read-out of the data of the address A1 of the ROM 2 is executed. An EEC circuit 3 inputs the data Dt1 and the bit PB8, respectively through a switching circuit 7 from the ROM 2 and the latch 8. Accordingly, the bit PB1 which has been stored in the address A1 is disregarded. Next, from the data Dt1, a regeneration parity bit PB1' is generated and set. In this state, when the circuit 3 operates normally, a failure bit is decided from exclusive OR of the PB1' and the PB8, and the data Dt1 is changed and outputted to a data I/O circuit 4. In such a way, a single test of the circuit 3 can be executed. |
