DETECTING CIRCUIT OF DIGITAL PLL STADE

摘要

The circuit is for preventing the error detection of the PLL state caused by a control voltage variation of a voltage controlled oscillator. The oscillating output of the VCO (13) is provided to a data input terminal (D) of a flip-flop (21) through a divider (14) and a reference signal is provided to a clock input terminal (CK). The output terminal (Q) of a D flip-flop (21) is connected to an input terminal (13) of a retriggerable one-shot multivirator (22) to provide logical high or low signal according to the locking state of the PLL.